题目

英语翻译
Accesses to slow external peripherals that do not have READY pin capable controls can
be accomplished by using the internal divided clock,flclk,as the timing source.Divid- ing hclk by 2,4,6,or 8 allows longer timing delays with the same programmable timing parameters.The Chip Select timing parameters are the same but the divided flclk is used
as the reference rather than hclk and all the transitions will occur with the rising edge of fclk with only full cycle delays

提问时间：2020-10-05

答案

如果要解决外部设备速度慢的问题,在没有准备好的可用PIN控件的情况下可以使用内置的分流时钟和时钟信号作为计时器.分流主时钟按照2,4,6,8的形式在同样的及时参数下允许更长的计时延迟.同样的芯片选择计时参数,但分流时钟信号用作参照而不是用作主时钟,而且所有的转换随着时钟信号上升沿在全循环延迟时发生.
我是做移民翻译的,这方面不大懂,大致是这个意思,